Fully parallel write/read in resistive synaptic array for accelerating on-chip learning-Reference-Cited by-同舟云学术

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Fully parallel write/read in resistive synaptic array for accelerating on-chip learning

Published:2015-10-22 Issue:45 Volume:26 Page:455204
ISSN:0957-4484
Container-title:Nanotechnology
language:
Short-container-title:Nanotechnology

Author:

Gao Ligang,Wang I-Ting,Chen Pai-Yu,Vrudhula Sarma,Seo Jae-sun,Cao Yu,Hou Tuo-Hung,Yu Shimeng

Publisher

IOP Publishing

Subject

Electrical and Electronic Engineering,Mechanical Engineering,Mechanics of Materials,General Materials Science,General Chemistry,Bioengineering

Link

http://stacks.iop.org/0957-4484/26/i=45/a=455204/pdf

Reference42 articles.

1. Neuromorphic Silicon Neurons and Large-Scale Neural Networks: Challenges and Opportunities

2. Finding a roadmap to achieve large neuromorphic hardware systems

3. The SpiNNaker Project

4. CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory–Processing– Learning–Actuating System for High-Speed Visual Object Recognition and Tracking

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