Radiation-hardened flip-flop for single event upset tolerance
Author:
Qi Chunhua,Ma Guoliang,Zhang Yanqing,Wang Tianqi,Rui Erming,Jiao Qiang,Liu Chaoming,Huo Mingxue,Zhai Guofu
Abstract
Purpose
The purpose of this paper is to present a transition detector (TD)-based radiation hardened flip-flop (TDRH-FF) for single event upset (SEU).
Design/methodology/approach
With SEU recovery and single event transient (SET) detector mechanism, the TDRH-FF can tolerate SEU during hold mode and generate a warning signal for architecture-level recovery during transport mode when input signal contains SET. Evaluation results show that the TDRH-FF outperforms comparable comprehensive performance.
Findings
Simulation results show that 1) the mean pulse width of the correction glitches (at full width half maximum) of TDRH-FF is less than 10 ps; 2) the area overhead of TDRH-FF is similar to the EVFERST-FF, BISER-FF and DNURHL-FF; 3) TDRH-FF has the same average power consumption as SETTOF, and moderate PDP and Ps values among these compared FFs.
Originality/value
In this paper, a TD-based TDRH-FF is proposed to solve the problems in the previous design. And the main contributions of the proposed TDRH-FF are summarized: Minimum size transistors are used in the proposed TD which leads to a considerable decrease in area overheads and propagation delay (resulting in an ignorable correction glitch); and compared with other radiation hardened flip-flop, TDRH-FF outperforms comparable comprehensive performance.
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference23 articles.
1. A double-node-upset self-recoverable latch design for high performance and low power application;IEEE Transactions on Circuits and Systems II: Express Briefs,2018
2. Bezdek, M. and Somani, A. (2006), “Utilizing timing error detection and recovery to dynamically improve superscalar processor performance”, MS thesis, Iowa State University.
3. Schemes for eliminating transient-width clock overhead from SET-tolerant memory-based systems;IEEE Transactions on Nuclear Science,2006
4. Error-correcting codes for semiconductor memory applications: a state-of-the-art review;IBM Journal of Research and Development,1984
5. Razorii: in situ error detection and correction for pvt and ser tolerance;IEEE Journal of Solid-State Circuits,2009