Transition time considerations in repeater‐chains-Reference-Cited by-同舟云学术

Transition time considerations in repeater‐chains

Published:2005-12-01 Issue:3 Volume:22 Page:39-40
ISSN:1356-5362
Container-title:Microelectronics International
language:en
Short-container-title:

Author:

Chandel Rajeevan,Sarkar S.,Agarwal R.P.

Abstract

PurposeIn this short communication, transition times of input signals for various stages of a repeater‐chain loaded VLSI interconnects are studied.Design/methodology/approachSPICE simulations.FindingsIt is observed that for a fixed number of repeaters a smaller load will reduce transition time. The effect is not very significant, if the load is moderate.Originality/valueMethod can be very useful for short‐circuit power estimation in repeater‐chains.

Publisher

Emerald

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference8 articles.

1. Adler, V. and Friedman, E.G. (1998), “Repeater design to reduce delay and power in resistive interconnects”, IEEE Transaction on Circuits and Systems‐II: Analog and Digital Signal Processing, Vol. 45 No. 5, pp. 607‐16.

2. Bakoglu, H.B. (1990), Circuits, Interconnections and Packaging for VLSI, Addison‐Wesley VLSI Systems Series, Reading, MA.

3. Banerjee, K. and Mehrotra, A. (2002), “A power‐optimal repeater insertion methodology for global interconnects in nanometer designs”, IEEE Transactions on Electron Devices, Vol. 49 No. 11, pp. 2001‐7.

4. Chandel, R., Sarkar, S. and Agarwal, R.P. (2005a), “Performance controlling parameters of voltage‐scaled repeaters for long interconnects”, IETE Journal of Research, Vol. 51 No. 2.

5. Chandel, R., Sarkar, S. and Agarwal, R.P. (2005b), “Repeater insertion in global interconnects in VLSI circuits”, Microelectronics International, Vol. 22 No. 1, pp. 43‐50.

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