Dual‐rail improved adiabatic pseudo‐domino logic with auxiliary clock: a low‐power partially‐adiabatic CMOS logic family-Reference-Cited by-同舟云学术

Dual‐rail improved adiabatic pseudo‐domino logic with auxiliary clock: a low‐power partially‐adiabatic CMOS logic family

Published:2003-08-01 Issue:2 Volume:20 Page:16-18
ISSN:1356-5362
Container-title:Microelectronics International
language:en
Short-container-title:

Author:

Tan W.M.,Lau K.T.

Abstract

An improved structure for adiabatic pseudo‐domino logic (APDL) family is presented in this paper. The modified dual‐rail improved APDL (MDIAPDL) exhibits lower power dissipation than the conventional static CMOS as shown in HSpice simulations. Comprehensive circuit simulations show that the MDIAPDL 4 bit shift register can recover over 95 per cent of the energy dissipated in conventional static CMOS 4 bit shift register.

Publisher

Emerald

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference6 articles.

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3. Maksimovic, D., Oklobdzija, V.G., Nikolic, B. and Current, K.W. (1997), Clocked CMOS adiabatic logic with integrated single‐phase power‐clock supply: experimental results, Proceedings of International Symposium on Low Power Electronics and Design, pp. 323‐7.

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1. Dual‐rail adiabatic pseudo domino logic with high throughput;Microelectronics International;2004-04