The Reduceron reconfigured and re-evaluated

Author:

NAYLOR MATTHEW,RUNCIMAN COLIN

Abstract

AbstractA new version of a special-purpose processor for running lazy functional programs is presented. This processor – the Reduceron – exploits parallel memories and dynamic analyses to increase evaluation speed, and is implemented using reconfigurable hardware. Compared to a more conventional functional language implementation targeting a standard RISC processor running on the same reconfigurable hardware, the Reduceron offers a significant improvement in run-time performance.

Publisher

Cambridge University Press (CUP)

Subject

Software

Reference30 articles.

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