Fully integrated three-way LDMOS Doherty PAs for 1.8–2.2 GHz dual-band and 2.6 GHz m-MIMO 5G applications

Author:

Vigneau MarcORCID,Ercoli Mariano,Maroldt Stephan

Abstract

AbstractThis paper presents a fully integrated three-way Doherty architecture to address the challenges of 5G applications using laterally-diffused metal-oxide semiconductor (LDMOS) technology. By using the so-called CDS cancelation method for the Doherty combiner design, a wideband impedance transformation is achieved, that combined with the three-way Doherty power amplifier (DPA) architecture allows for high efficiency in deep back-off, with a reduced load modulation for high bandwidth. Throughout this paper, the design approach and realization are described, while multiple critical design challenges will be addressed such as low frequency drain resonance optimization, impact of in-package coupling effects, and linearity versus efficiency tradeoff. Two state-of-the-art three-way fully integrated LDMOS DPA monolithic microwave integrated circuit (MMICs) are presented to demonstrate how these measures have been successfully applied to different power amplifier (PA) line-up components for 5G base station systems. First, a 60 W 1.8–2.2 GHz multi-stage device for driver application in true dual-band operation is presented. The circuit design pays special attention to extended PA video bandwidth thanks to integrated passive device. After digital pre-distortion (DPD) in dual-band operation, this highly linear device achieves an outstanding adjacent channel leakage ratio (ACLR) of −56 dBc for a 2cLTE 20 MHz 8 dB peak-to-average ratio signal spaced by 345 MHz, thus 385 MHz instantaneous bandwidth (IBW), with 29% efficiency at 35 dBm, 12 dB output back-off (OBO). Second, the simulation and measurement results of a 55 W 2.6 GHz multi-stage DPA for massive-MIMO final stage application are presented, which yields an excellent linearized efficiency of 49% using a 200 MHz 10cLTE signal with an ACLR lower than −47.5 dBc. For 8cLTE 20 MHz (160 MHz IBW), the device yields 50% efficiency with −50.7 dBc ACLR linearized after DPD. The achieved efficiency is well comparable to published GaN DPAs. These results were achieved by improved simulation techniques to minimize frequency dispersion and thus allow high efficiency operation over wide bandwidth. Both devices show that LDMOS is not only a mature technology which allows those PAs to be reliable and low-cost for mass production in very compact packages, but also provide best-in-class RF performance according to the needs of 5G base station systems.

Publisher

Cambridge University Press (CUP)

Subject

Electrical and Electronic Engineering

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Applicability of Channel Doping Gradient in the Design of a Short Channel (0.1 µm) LDMOS Transistor for Integrated Power and RF Applications;Transactions on Electrical and Electronic Materials;2024-04-04

2. Mathematically inspired MIMO antenna with enhanced isolation for wireless applications;International Journal of Communication Systems;2024-02-03

3. Study of AM-PM Deviation on Power Amplifier Linearization Performances for 5G Applications;2024 IEEE Topical Conference on RF/Microwave Power Amplifiers for Radio and Wireless Applications (PAWR);2024-01-21

4. Design of High-efficiency Continuous Class F Doherty Power Amplifier;Journal of Physics: Conference Series;2023-10-01

5. Study of High Frequency Nonlinear Memory Effect on Doherty Power Amplifiers Linearization Performances for 5G Applications;2023 IEEE Topical Conference on RF/Microwave Power Amplifiers for Radio and Wireless Applications;2023-01-22

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