A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

Author:

Torres FlorentORCID,Kerhervé Eric,Cathelin Andreia,De Matos Magali

Abstract

AbstractThis paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

Publisher

Cambridge University Press (CUP)

Subject

Electrical and Electronic Engineering

Reference11 articles.

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5. 5. Torres, F , De Matos, M , Cathelin, A and Kerhervé, E (2018) A 31 GHz 2-Stage Reconfigurable Balanced Power Amplifier with 32.6 dB Power Gain, 25.5% PAEmax and 17.9 dBm Psat in 28 nm FD-SOI CMOS, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Philadelphia, PA, pp. 236–239.

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