Author:
Sobotta Elena,Belfiore Guido,Ellinger Frank
Abstract
This work presents the design of two compact multi-standard low-noise amplifier (LNA) in a 28 nm low-power bulk CMOS process. The transistor parameters were optimized by the gm/ID method taking into account the parasitics and the behavior of highly scaled transistors. To cover the industrial science medical (ISM)-bands around 2.4 and 5.8 GHz, the WLAN band as well as the Ku band a bandwidth enhancement is required. Two versions of LNAs, one with vertical inductors and one with active inductors, are implemented and verified by measurements. The noise figure (NF) exhibits 4.2 dB for the LNA with active inductors and 3.5 dB for the LNA with vertical inductors. The voltage gain reaches 12.8 and 13.4 dB, respectively, with a 3 dB-bandwidth of 20 GHz. Both input referred 1-dB-compression points are higher than −12 dBm making the chips attractive for communication standards with high linearity requirements. The chips consume 53 mW DC power and the LNA with active inductors occupies a core area of only 0.0018 mm2, whereas the version with vertical inductors requires 0.021 mm2.
Publisher
Cambridge University Press (CUP)
Subject
Electrical and Electronic Engineering
Reference18 articles.
1. A dual-band balun LNA resilient to 5–6 GHz WLAN blockers for IR-UWB in 65nm CMOS
2. Power efficient distributed low-noise amplifier in 90 nm CMOS;Machiels;IEEE Radio Frequency Integrated Circuits Symp., Technical Reports,2010
3. CMOS LNA design at 30 GHz, a case study;Antonopoulos;8th Int. Caribbean Conf. on Devices, Circuits and System,2012
4. A 55-GHz-bandwidth track-and-hold amplifier in 28-nm low-power CMOS;Tretter;IEEE Tran. Circuits Systems II: Express Briefs,2015
5. A 65 nm CMOS Wide-band LNA with Continuously Tunable Gain from 0 dB to 24 dB;Sturm;IEEE Int. Symp. on Circuits and Systems,2013
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