OPTIMIZATION OF CHARGE / DISCHARGE TIME OF ACTIVE FILTER CAPACITORS DURING VOLTAGE FLUCTUATIONS

Abstract

A voltage regulator on capacitors has been developed for the control circuit of a parallel active filter based on dq-theory with a block of sliding averaging current in the current control circuit i_d. It contains a delay unit, a digital low-pass filter of the first order FIR or IIR (depending on the variant of the considered scheme) and the unit “sgn”, which stabilizes the output signal. The voltage control circuit on the capacitor can be implemented entirely in digital signal processing and used instead of the analog PID controller, which is much more effective if you need to adapt the circuit to the load mode. Most analog filters suffer from phase distortion when signals at different frequencies are delayed by different amounts. Although it is still present in digital IIR filters. FIR filters are usually designed as a “linear phase”, which means that the filter has no phase distortion. Phase distortions occur due to the fact that signals of different frequencies are delayed differently when crossing the filter. For IIR filters, it is necessary to enter an additional factor that will regulate the group delay, during which the filter will delay the signal of a certain frequency. If you do the same for the FIR filter, you will see a straight horizontal line, which means that all signals are delayed by the same amount, which is good and will provide better signal quality. The unit “sgn” does not affect the process of maintaining the voltage on the capacitors and the speed of transients, its role is to enhance the compensatory capacity of the voltage regulator by filtering the digital signal. The selected filter, by automatically stabilizing the voltage on the capacitor provides a stable charge / discharge process of the capacitor and a high level of compensation of higher harmonics without significant additional generation of active power in the network. When used in the context of real-time analog systems, the digital filter sometimes has a problematic delay (input-output time difference) due to analog-to-digital and digital-to-analog conversion and smoothing. It is shown that by optimizing the charge / discharge time of the capacitor of the power active filter it is possible to achieve the minimum duration of the transient process with the minimum values of harmonic distortions.