Copper Content Optimization for Asymmetric Package Substrate Warpage by Genetic Algorithm-Reference-Cited by-同舟云学术

Copper Content Optimization for Asymmetric Package Substrate Warpage by Genetic Algorithm

Published:2023-11-10 Issue:6 Volume:12 Page:306-313
ISSN:2186-702X
Container-title:Journal of Smart Processing
language:en
Short-container-title:

Author:

MORI Hiroyuki¹

Affiliation:

1. Chiplet Interconnect, Semiconductors, IBM Research-Tokyo, IBM Japan, Ltd.

Publisher

Sumart Processing Society for Minerals, Environment and Energy

Subject

Industrial and Manufacturing Engineering,Surfaces, Coatings and Films

Link

https://www.jstage.jst.go.jp/article/jspmee/12/6/12_306/_pdf

Reference7 articles.

1. 1） Universal Chiplet Interconnect Express: “Universal Chiplet Interconnect Express （UCIe） Specification Revision 1.0”, https:// www.uciexpress.org/team-3, （2022）, 15-25.

2. 2） Chang-Chi Lee, Cp Hung, Calvin Cheung, Ping-Feng Yang, Chin- Li Kao, et al.: “An Overview of the Development of a GPU with Integrated HBM on Silicon Interp oser”, 2016 IEEE 66th Electronic Components and Technology Conference （ECTC）, （2016）, 1439- 1444.

3. 3） N. Shimizu, W. Kaneda, H. Arisaka, N. Koizumi, S. Sunohara, A. Rokugawa and T. Koyama: “Development of Organic Multi Chip Package for High Performance Application”, 46th International Symposium on Microelectronics （IMAPS 2013）, （2013）, 414-419.

4. 4） H. Mori and S. Kohara: “Copper Content Optimization for Warpage Minimization of Substrates with an Asymmetric Cross-Section by Genetic Algorithm”, 2021 IEEE 71st Electronic Components and Technology Conference （ECTC）, （2021）, 1521-1526.

5. 5） H. Mori and S. Kohara: “Design Optimization for Cavity Substrate Warpage for HBM Applications”, 31st Microelectronics Symposium （MES）, 31, （2021）, 179-182. （in Japanese）