Evaluation of Thermal Resistance for Underfill Layer in Three-dimensional Stacked ICs by Transient Thermal Analysis
Author:
Affiliation:
1. Fujitsu Limited
Publisher
Sumart Processing Society for Minerals, Environment and Energy
Link
https://www.jstage.jst.go.jp/article/jspmee/7/4/7_122/_pdf
Reference9 articles.
1. A. Horibe, K. Okamoto, H. Mori, Y. Orii, K. Kawase, Y. Takamatsu, “Thermally enhanced pre-applied underfills for 3D integration”, 2013 IEEE 63rd Electronic Components and Technology Conference (ECTC), 2013, 909-914.
2. K. Matsumoto, H. Mori, Y. Orii, H. Kiritani, Y. Kawase, M. Ikemoto, M. Yamazaki, M. Sugiyama, F. Mizutani, “High thermal conductivity underfill for the thermal management of three-dimensional (3D) chip stacks,” 2014 IEEE 30th Semiconductor Thermal Measurement & Management Symposium (SEMI-THERM), 2014, 219-223
3. H. Oprins, V. Cherman, K. J. Rebibis, K. Vermeersch, C. Gerets, B. Vandevelde, A. La Manna, G. Beyer, E. Beyne, “Transient analysis based thermal characterization of die-die interfaces in 3D-ICs,” 2012 IEEE 13th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2012, 1395-1404.
4. S. Nakanekar, A. Kaisare, S. Tonapi, “Optimal thermal characterization of a stacked die package with TSV technology,” 2012 IEEE 13th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2012, 130-136.
5. Y. Kim, SB Park, “Optimization of underfill material for better reliability and thermal behavior of 3D packages with TSVs”, 2013 IEEE 63rd Electronic Components and Technology Conference (ECTC), 2013, 2310-2318.
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