Barrier synchronization hierarchical algorithm for multicore shared-memory systems-Reference-Cited by-同舟云学术

Barrier synchronization hierarchical algorithm for multicore shared-memory systems

Published:2022-07-22 Issue:2 Volume: Page:3-11
ISSN:1998-6920
Container-title:The Herald of the Siberian State University of Telecommunications and Informatics
language:
Short-container-title:jour

Author:

Kurnosov M. G.¹

Affiliation:

1. Siberian State University of Telecommunications and Information Science

Abstract

A hierarchical MPI barrier synchronization algorithm creating groups of processes that share common resources at the memory hierarchy levels (L2/L3 caches, NUMA node, socket) is proposed. Synchronization is performed in groups at each level of the hierarchy. Experiments on a dual-socket server with two Huawei Kunpeng processors (128 cores, 4 NUMA nodes) showed that the proposed algorithm with NUMA nodes process grouping provides the minimum execution time compared to known methods and is resistant to different schemes of process placement.

Publisher

Siberian State University of Telecommunications and Informatics

Reference6 articles.

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