Modeling of Thermal Processes in “Package-on-Package” Type Multichip Microcircuits-Reference-Cited by-同舟云学术

Modeling of Thermal Processes in “Package-on-Package” Type Multichip Microcircuits

Published:2021-07 Issue:7 Volume:92 Page:369-374
ISSN:1068-3712
Container-title:Russian Electrical Engineering
language:en
Short-container-title:Russ. Electr. Engin.

Author:

Belyaev M. A.,Putrolainen V. V.,Seredov P. N.,Lunkov P. V.

Publisher

Allerton Press

Subject

Electrical and Electronic Engineering

Link

https://link.springer.com/content/pdf/10.3103/S106837122107004X.pdf

Reference14 articles.

1. Mamaluy, D. and Gao, X., The fundamental downscaling limit of field effect transistors, Appl. Phys. Lett., 2015, vol. 106, no. 19.

2. 3D Flash Memories, Micheloni, R., Ed., Dordrecht: Springer-Verlag, 2016.

3. Lau, J.H., 3D IC Integration and Packaging, New York: McGraw-Hill, 2016.

4. Lau, J.H., Fan-Out Wafer-Level Packaging, Singapore: Springer-Verlag, 2018.

5. Yoshida, A., Taniguchi, J., Murata, K., Kada, M., Yamamoto, Y., Takagi, Y., Notomi, T., and Fujita, A., A study on package stacking process for package-on-package (PoP), Proc. 56th Electronic Components and Technology Conf., Piscataway, NJ: Inst. Electr. Electron. Eng., 2006, vol. 1.

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