Author:
Samanta Jagannath,Bhaumik Jaydeb,Barman Soma
Subject
Electrical and Electronic Engineering
Reference18 articles.
1. E. R. Berlekamp, “Bit-serial Reed-Solomon encoders,” IEEE Trans. Inf. Theory 28, No. 6, 869 (Nov. 1982), DOI: 10.1109/TIT.1982.1056591.
2. Tong Zhang, K. K. Parhi, “Systematic design of original and modified Mastrovito multipliers for general irreducible polynomials,” IEEE Trans. Comput. 50, No. 7, 734 (Jul. 2001), DOI: 10.1109/12.936239.
3. R. Reyhani-Masoleh, M. A. Hasan, “A new construction of Massey-Omura parallel multiplier over GF(2m),” IEEE Trans. Comput. 51, No. 5, 511 (May 2002), DOI: 10.1109/TC.2002.1004590.
4. C. C. Wang, T. K. Truong, H. M. Shao, L. J. Deutsch, J. K. Omura, I. S. Reed, “VLSI architectures for computing multiplications and inverses in GF(2m),” IEEE Trans. Comput. C–34, No. 8, 709 (Aug. 1985), DOI: 10.1109/TC.1985.1676616.
5. Zhijie Jerry Shi, Hai Yun, “Software implementations of elliptic curve cryptography,” Int. J. Network Security 7, No. 1, 141 (2008), http://ijns.jalaxy.com.tw/download_paper.jsp?PaperID=IJNS-2006-09-13-3&PaperName=ijns-v7-n1/ijns-2008-v7-n1-p141-150.pdf.