Author:
Riera B.,Philippot A.,Annebicque D.,Gellot F.
Reference19 articles.
1. Barragan Santiago I., Roth M., Faure J.M., (2006). Obtaining temporal and timed properties of logic controllers from fault tree analysis, 12th IFAC Symposium on Information Control Problems in Manufacturing, Saint-Etienne, France, pp. 243-248
2. Benlorhfar R., Annebicque D., Gellot F., Riera B. (2011). Robust filtering of PLC program for automated systems of production, 18th World Congress of the International Federation of Automatic Control, Milano, Italy, august.
3. Behrmann G., Bengtsson J., David A., Larsen K.G., Pettersson P., Yi W. (2002) Uppaal implementation secrets. 7th International Symposium on Formal Techniques in Real-Time and Fault Tolerant Systems.
4. Canet G., Couffin S., Lesage J.-J., Petit A., (2000) Schnoebelen P., Toward the automatic verification of PLC programs written in instruction list, EE International Conference on Systems Man and Cybernetics, Nashville, USA, pp. 2449-2454.
5. Introduction ti discrete event systems;Cassandra,1999
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献