A Fault Tolerant Design Methodology for a FPGA-based Softcore Processor

Author:

Garcia P.,Gomes T.,Salgado F.,Cabral J.,Cardoso P.,Ekpanyapong M.,Tavares A.

Publisher

Elsevier BV

Subject

General Medicine

Reference22 articles.

1. Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement;Argyrides;14th IEEE International On-Line Testing Symposium,2008

2. Design of a robust 8-bit microprocessor to soft errors;Bastos;12th IEEE International On-Line Testing Symposium,2006

3. Carmichael, C., Fuller, E., Fabula, J., Lima, F., (2001). Proton Testing of SEU Mitigation Methods for the Virtex FPGA. Proc. of Military and Aerospace Applications of Programmable Logic Devices MAPLD.

4. Robust Register Caching: An Energy-Efficient Circuit-Level Technique to Combat Soft Errors in Embedded Processors;Fazeli;IEEE Transactions on Device and Materials Reliability,2010

5. Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level;Fernández-Pascual;IEEE Transactions on Parallel and Distributed Systems,2010

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