Performance analysis of carrier depletion silicon PIN phase shifter
Author:
Ramesh Gabriel Jesuwanth Sugesh1, Arunagiri Sivasubramanian1
Affiliation:
1. School of Electronics Engineering, Vellore Institute of Technology , Chennai , Tamil Nadu , India
Abstract
Abstract
In this paper, we report the performance of a carrier depletion Silicon PIN phase shifter with over layer of 130 nm. It is observed that an optimum intrinsic gap of 250 nm for a device length of 5 mm at 2 V, resulted in Extinction Ratio (ER) of 23.41 dB and Bit Error Rate (BER) of 1.00 × 10−7 is obtained for 50 Gbps. The phase shifter is also designed for length 2 mm with an intrinsic gap of 100 nm at an operating voltage <4 V. The study also reveals that the proposed design for Mach-Zehnder modulator operating at a data rate of 100 Gbps for the concentration of P = 7 × 1017 cm−3 and N = 5 × 1017 cm−3 gives better BER and phase performance. The proposed design was also analysed in an intra-data centre communication setup of fibre length 15 km.
Publisher
Walter de Gruyter GmbH
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Atomic and Molecular Physics, and Optics
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