FPGA Implementation of Multi-scale Face Detection Using HOG Features and SVM Classifier

Author:

Drożdż Michał1,Kryjak Tomasz1

Affiliation:

1. AGH University of Science and Technology, al. Mickiewicza 30, 30-059 Kraków

Abstract

Abstract In this paper an FPGA based embedded vision system for face detection is presented. The sliding detection window, HOG+SVM algorithm and multi-scale image processing were used and extensively described. The applied computation parallelizations allowed to obtain real-time processing of a 1280 × 720 @ 50Hz video stream. The presented module has been verified on the Zybo development board with Zynq SoC device from Xilinx. It can be used in a vast number of vision systems, including diver fatigue monitoring.

Publisher

Walter de Gruyter GmbH

Reference25 articles.

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4. [4] Das, S., Jariwala, A., Engineer, P. (2012). Modified architecture for real-time face detection using FPGA. In Engineering (NUiCONE), 2012 Nirma University International Conference on, pp. 1–5

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