An enhanced implementation of SRF and DDSRF-PLL for three-phase converters in weak grid

Abstract

Abstract Renewable energy generation systems connected to utility grid require perfect synchronization to grid which is one of the most important issues that needs to be taken into consideration. This paper proposed a hardware-accelerated implementation for the decoupled double synchronous reference frame phase-locked loop (DDSFR-PLL) for grid synchronization in grid-connected converters in weak grid that suffers from phase voltage-unbalance, variable phase and frequency conditions. Since the transformations and filtering of this method is computationally intensive and needs to be executed as fast as possible by the microcontroller unit (MCU) and Due to the presence of other current and voltage regulation loops in the same interrupt service routine (ISR) with high frequency rate, a hardware-based acceleration using the STM32G4x4 MCU built-in filter, filter math accelerator (FMAC) and coordinate rotation digital computer (CORDIC) is used to speed the execution time. This study addresses the description, derivation and implementation of the both DQ-PLL and DDSRF-PLL algorithms. The performance of both pure-software and accelerated implementation is demonstrated, compared and run on a three-level active neutral point clamped (ANPC) converter board. In proposed method, CPU load dropped from 80.5% by using the conventional software implementation to 23.6% (70% load reduction).This reduction in CPU load enables the addition of more features and more advanced current and voltage control algorithms.