Semi-formal verification of closed-loop specifications in the concept design phase

Abstract

Abstract The article addresses the semi-formal verification of behavioral specifications for subsystems consisting of physical parts and controllers, complemented by simulation-based integration testing. Since design errors in early phases tend to be particularly expensive, the method is tailored towards applicability in these phases. We verify behavioral specifications with proof-like credibility, or falsify them while providing a violation scenario that is reusable as a test case. The system is represented as a mixed logical dynamical (MLD) system, and specifications are expressed by a temporal logic with affine signal abstractions. The verification problem is converted into an equivalent mixed-integer linear feasibility problem solved using off-the-shelf solvers. An example illustrates the effectiveness of the method.