Asynchronous Wrapper-Based Low-Power GALS Structural QDMA-Reference-Cited by-同舟云学术

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Asynchronous Wrapper-Based Low-Power GALS Structural QDMA

Published:2022-01-24 Issue: Volume: Page:1-10
ISSN:0377-2063
Container-title:IETE Journal of Research
language:en
Short-container-title:IETE Journal of Research

Author:

Vinay B.K.¹²^ORCID,Pushpa Mala S.²,Deekshitha S.³

Affiliation:

1. Department of Electronics and Communication Engineering, Vidyavardhaka College of Engineering, Mysuru 570002, India

2. Department of Electronics and Communication, Dayananda Sagar University, Bangalore, Karnataka 560114, India

3. CMR Institute of Technology, Bangalore, Karnataka 560037, India

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering,Computer Science Applications,Theoretical Computer Science

Link

https://www.tandfonline.com/doi/pdf/10.1080/03772063.2021.2021814

Reference19 articles.

1. Clock distribution networks in synchronous digital integrated circuits

2. J. Muttersbach, “Globally-asynchronous locally-synchronous architectures for VLSI systems,” Ph.D. thesis, ETH, Zurich, 2001.

3. System integration by request-driven GALS design

4. Design Of An Improved And Robust Asynchronous Wrapper (Aw) For FPGA Applications

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