Efficient CNN Accelerator on FPGA-Reference-Cited by-同舟云学术

Efficient CNN Accelerator on FPGA

Published:2020-09-24 Issue:6 Volume:66 Page:733-740
ISSN:0377-2063
Container-title:IETE Journal of Research
language:en
Short-container-title:IETE Journal of Research

Author:

Kala S¹,Nalesh S²

Affiliation:

1. Department of Electronics and Communication Engineering, Indian Institute of Information Technology Kottayam, Kottayam India

2. Department of Electronics, Cochin University of Science And Technology, Cochin, India

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering,Computer Science Applications,Theoretical Computer Science

Link

https://www.tandfonline.com/doi/pdf/10.1080/03772063.2020.1821797

Reference23 articles.

1. Y. Ma, Y. Cao, S. Vrudhula, and J. Seo, “An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks,” in 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, 2017, pp. 1–8.

2. A. Podili, C. Zhang, and V. Prasanna, “Fast and efficient implementation of Convolutional Neural Networks on FPGA,” in IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Seattle, WA, 2017, pp. 11–18.

3. Y. Guan, H. Liang, N. Xu, W. Wang, S. Shi, X. Chen, G. Sun, W. Zhang, and J. Cong, “FP-DNN: An automated framework for mapping deep neural networks onto FPGAs with RTL-HLS hybrid templates,” in IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, 2017, pp. 152–9.

4. Q. Xiao, Y. Liang, L. Lu, S. Yan and Y-W. Tai, “Exploring heterogeneous algorithms for accelerating deep convolutional neural networks on FPGAs,” in 54th ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, 2017, pp. 1–6.

5. H. Li, X. Fan, L. Jiao, W. Cao, X. Zhou, and L. Wang, “A high performance FPGA-based accelerator for large-scale convolutional neural networks,” in 26th International Conference on Field Programmable Logic and Applications (FPL), Lausanne, 2016, pp. 1–9.

Cited by 20 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Implementation of Image Compression Based on FPGA;2024 5th International Seminar on Artificial Intelligence, Networking and Information Technology (AINIT);2024-03-29

2. Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects;Alexandria Engineering Journal;2024-03

3. An Accelerated FPGA-Based Parallel CNN-LSTM Computing Device;IEEE Access;2024

4. Approximate CNN on FPGA Using Toom-Cook Multiplier;2023 IEEE International Symposium on Smart Electronic Systems (iSES);2023-12-18

5. Fully Pipelined FPGA Acceleration of Binary Convolutional Neural Networks with Neural Architecture Search;Journal of Circuits, Systems and Computers;2023-12-08