A High-Speed, Low-Power, and Area-Efficient FGMOS-Based Full Adder
Author:
Affiliation:
1. Department of Electronics, University of Jammu, Jammu, India
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering,Computer Science Applications,Theoretical Computer Science
Link
https://www.tandfonline.com/doi/pdf/10.1080/03772063.2019.1700833
Reference14 articles.
1. Advances in Logic Device Scaling
2. Floating-gate MOS Structures and Applications
3. Design of high speed and low power 4-bit comparator using FGMOS
4. Split length FGMOS MOS cell: a new block for low voltage applications
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