High-Performance 10-Transistor Adder Cell for Low-Power Applications-Reference-Cited by-同舟云学术

High-Performance 10-Transistor Adder Cell for Low-Power Applications

Published:2022-03-07 Issue: Volume: Page:1-19
ISSN:0377-2063
Container-title:IETE Journal of Research
language:en
Short-container-title:IETE Journal of Research

Author:

Misra Aishani¹,Birla Shilpi¹^ORCID,Singh Neha¹,Dargar Shashi Kant²

Affiliation:

1. Department of Electronics & Communication Engineering, Manipal University Jaipur, Jaipur 303007, India

2. Department of Electronics & Communication Engineering, Kalasalingam Academy of Research and Education, Tamilnadu 626126, India

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering,Computer Science Applications,Theoretical Computer Science

Link

https://www.tandfonline.com/doi/pdf/10.1080/03772063.2022.2043785

Reference29 articles.

1. Misra Aishani, Shilpi Birla, and Neha Singh, “Comparative analysis of various adder architectures on 28 nm CMOS technology,” in 2020 7th International Conference on Computing for Sustainable Global Development (INDIACom). pp. 73–76. IEEE, 2020.

2. Misra Aishani, Shilpi Birla, and Neha Singh. Performance Analysis and Comparison of 4-Bit Adder Architectures. London: Intelligent Circuits and Systems, CRC Press, pp. 41–45, 2021.

3. Ajit Anaswar, P.V. Arathi, Kiran Haridas, Niraj Mohan Nambiar, and S. Devi, “FPGA based performance comparison of different basic adder topologies with parallel processing adder,” in 2019 3rd International Conference on Electronics, Communication and Aerospace Technology (ICECA). IEEE, 2019.

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