Performance Analysis of Data-Driven Pipelined Computer Architectures

Author:

Chi Kuang-Hwei1,Tseng Chien-Chao1,Lin Chih-Zong1,Chou Wen-Kuang2

Affiliation:

1. Department of Computer Science and Information Engineering, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu, Taiwan 30050; e-mail: {, , }

2. Department of Information Science, Providence University, 200 Chung-chi Road, Shalu, Taichung, Taiwan 433;

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Mechanics of Materials,Modelling and Simulation,Software

Reference13 articles.

1. D.E. Culler, K.E. Schauser, & Thorsten von Eicken, Two fundamental limits on dataflow multiprocessing,IFIP Working Conf. on Architecture and Compilation Techniques for Fine and Midium Grain Parallelism, Orlando, FL, 1993, 153–164.

2. Arvind & R.A. Iannucci, A critique of multiprocessing von Neumann style,Proc. 10th Ann. Symp. Computer Architecture Symp., New York, NY, 1983, 426–436.

3. Arvind & R.A. Iannucci, Two fundamental issues in multiprocessing,Computation Structures Group Memo 226-6, 1987.

4. G.M. Papadopoulos & D.E. Culler, Monsoon: An explicit token-store architecture,1990 Symp. on Computer Architecture, Los Alamitos, CA, 1990, 82–91.

5. S. Sakai, Y. Yamaguchi, K. Hiraki, Y. Kodama, & T. Yuba, An architecture of a dataflow single chip processor,Proc. 16th Ann. Symp. on Computer Architecture, Washington, DC, 1989, 46–53.

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