Delay-Macromodelling Of Cmos Transmission-Gate-Based-Circuits
Author:
Affiliation:
1. Department of Electrical Engineering, City College of New York, New York, NY, 10031, USA,
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Mechanics of Materials,Modelling and Simulation,Software
Link
https://www.tandfonline.com/doi/pdf/10.1080/02286203.1995.11760258
Reference13 articles.
1. M. D. Matson & L. A. Glasser, ‘Macromodeling and optimization of digital MOS VLSI circuits, IEEE Trans, on Computer-Aided Design, CAD-5(10), 1986,659–678.
2. D. Deschacht, M. Robert, & D. Auvergne, Explicit formulation of delays in CMOS data paths, IEEE J. Solid-State Circuits, SC-23(5), 1988, 1257–1264.
3. L. Brocco, S. P. McCormick, & J. Allen, Macromodeling CMOS circuits for timing simulation, IEEE Trans, on Computer-Aided Design, CAD-7(12), 1988, 1237–1249.
4. C. Y. Wu & J. S. Hwang, 'Efficient timing models of small-geometry CMOS inverters and multi-input NAND/NOR gates and their applications, Solid-State Electronics, 32(6), 1989, 449–467.
5. H. G. Yang & D. M. Ilolbum, Switch-level timing verification for CMOS circuits: a semianalytic approach, IEE Proc, Part G, 137(6), 1990, 405–412.
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