Testable Design of Digital Summation Threshold Logic Array for Synthesis of Symmetric Functions

Author:

Rahaman H.1,Das D.K.2,Bhattacharya B.B.3

Affiliation:

1. Information Technology, Bengal Engineering and Science University, Shibpur, Howrah 711 103, India;

2. Computer Science and Engineering, Jadavpur University, Calcutta 700 032, India;

3. ACM Unit Indian Statistical Institute, Calcutta 700 108, India;

Publisher

Informa UK Limited

Subject

Computer Graphics and Computer-Aided Design,Computer Science Applications,Hardware and Architecture,Software

Reference13 articles.

1. S.L. Hurst, Digital summation threshold logic gates: A new circuit element,IEE Proc, 120(11), 1973, 1301–1307.

2. W. Ke & P.R. Menon, Delay-testable implementations of symmetric functions,IEEE Trans. on CAD, 14, 1995, 772–775.

3. S. Chakraborty, S. Das, D.K. Das, & B.B. Bhattacharya, Synthesis of symmetric functions for path-delay fault testability,IEEE Trans. on CAD, 19, 2000, 1076–1081.

4. Z. Kohavi,Switching and finite automata theory(New York: McGraw-Hill, 1977).

5. J. Ja'Ja' & S.M. Wu, A new approach to realize partially symmetric functions,Technical Report SRC TR 86-54, Department of Electrical Engineering, University of Maryland, 1986.

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