A Multi-Path Routing Scheme for Torus-Based NOCs
Author:
Affiliation:
1. College of Information Technology and Science, Nankai University, China; e-mails:
2. Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, USA; e-mail: {, }
Publisher
Informa UK Limited
Subject
Computer Graphics and Computer-Aided Design,Computer Science Applications,Hardware and Architecture,Software
Link
https://www.tandfonline.com/doi/pdf/10.1080/1206212X.2008.11441874
Reference8 articles.
1. A. Jantsch & H. Tenhunen,Networks on chip(Norwell, MA: Kluwar Academic Publishers, 2003).
2. W.J. Dally,A VLSI architecture for concurrent data structures, Ph.D. Dissertation, California Institute of Technology, 1986.
3. N. Kavaldjiev & G.M. Smit, An energy-efficient network-on-chip for a heterogeneous tiled reconfigurable systems-on-chip,Proc. Euromicro Symp. Digital System Design (DSD), Rennes, France, 2004, 492–498.
4. J.P. Uyemura, Introduction toVLSI circuits and systems(New York: John Wiley & Sons, 2002).
5. J. Duato, S. Yalamanchili, & L. Ni,Interconnection networks: An engineering approach(San Francisco, CA: Morgan Kaufmann Publishers, 2003).
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