Power Efficiency and Latency for a Semi-Batch Power Management Model in a Palmtop Multimedia Terminal

Author:

Hu J.R.1,Bai Y.W.1

Affiliation:

1. Department of Electronic Engineering, Fu Jen Catholic University, Taipei, Taiwan, 242;

Publisher

Informa UK Limited

Subject

Computer Graphics and Computer-Aided Design,Computer Science Applications,Hardware and Architecture,Software

Reference5 articles.

1. S. Shigematsu, S. Mutoh, & Y. Matsuya, Power management technique for 1-V LSIs using embedded processor, IEEE 1996 Custom Integrated Circuits Conf., San Diego, CA, 1996, 111-114.

2. J.M. Rulnick & N. Bambos, Mobile power management for maximum battery life in wireless communication network, Proc. IEEE INFOCOM V2, San Francisco, CA, 1996, 443-450.

3. A. Raghunathan & N.K. Jha, Behavior synthesis for low power, ICCD'94, Proc, Cambridge, MA, 1994, 318-322.

4. Z.J. Lemnios & K.J. Gabriel, Low-power electronics, IEEE Design & Test of Computers, Winter, 1994, 8-13.

5. Hsiao-ping Juan, Viraphol Chaiyakul & Daniel D. Gajski, Condition graphs for high-quality behavioral synthesis, Proc. ACM, 1994, 170-174.

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