Flexible FPGA 1D DCT hardware architecture for HEVC-Reference-Cited by-同舟云学术

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Flexible FPGA 1D DCT hardware architecture for HEVC

Published:2023-07-04 Issue:4 Volume:64 Page:886-892
ISSN:0005-1144
Container-title:Automatika
language:en
Short-container-title:Automatika

Author:

Mlinarić Hrvoje¹,Duspara Alen¹,Hofman Daniel¹,Knezović Josip¹

Affiliation:

1. Faculty of Electrical Engineering and Computing, University of Zagreb, Zagreb, Croatia

Funder

European Regional Development Fund

Publisher

Informa UK Limited

Subject

General Computer Science,Control and Systems Engineering

Link

https://www.tandfonline.com/doi/pdf/10.1080/00051144.2023.2228580

Reference24 articles.

1. Overview of the High Efficiency Video Coding (HEVC) Standard

2. Bross B Han W-J Sullivan GJ et al. High efficiency video coding (HEVC) text specification draft 9 document JCTVC-K1003 ITU-T/ISO/IEC joint collaborative team on video coding (JCT-VC) Oct. 2012.

3. Video codec for audiovisual services at px64 kbit/s ITU-T Rec. H.261 version 1: Nov. 1990 version 2: Mar. 1993.

4. Video coding for low bit rate communication ITU-T Rec. H.263 Nov. 1995 (and subsequent editions).

5. Coding of moving pictures and associated audio for digital storage media at up to about 1.5 Mbit/s—part 2: video ISO/IEC 11172-2 (MPEG-1) ISO/IEC JTC 1 1993.

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