Optimization of printed circuit board interconnectivity testing for parallel devices-Reference-Cited by-同舟云学术

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Optimization of printed circuit board interconnectivity testing for parallel devices

Published:2017-01-26 Issue:10 Volume:49 Page:1750-1760
ISSN:0305-215X
Container-title:Engineering Optimization
language:en
Short-container-title:Engineering Optimization

Author:

Mo Jeonghoon¹

Affiliation:

1. Department of Information and Industrial Engineering, Yonsei University, Seoul, Korea

Publisher

Informa UK Limited

Subject

Applied Mathematics,Industrial and Manufacturing Engineering,Management Science and Operations Research,Control and Optimization,Computer Science Applications

Link

https://www.tandfonline.com/doi/pdf/10.1080/0305215X.2017.1281609

Reference13 articles.

1. Optimization of printed circuit board manufacturing: Integrated modeling and algorithms

2. Complexity on Parallel Machine Scheduling: A Review

3. An improved technique for circuit board interconnect test

4. Chen, L. 2007. “Study on Interconnect Test Generation of MCMBased on Particle Swarm Optimization Algorithm and Genetic Algorithm.” In 8th International Conference on Electronics Packaging Technology, edited by Ming Li, 1–4. IEEE.

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