Architecture-level energy model for high-capacity STT-MRAM memory
Author:
Affiliation:
1. Department of Electrical Engineering, School of Internet-of-Things (IoTs), Jiangnan University, Wuxi, China
Funder
National Natural Science Foundation of China
Publisher
Informa UK Limited
Link
https://www.tandfonline.com/doi/pdf/10.1080/00207217.2024.2312561
Reference17 articles.
1. 4Gbit density STT-MRAM using perpendicular MTJ realized with compact cell structure
2. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
3. Eken, E., Song, L., Bayram, I., Xu, C., Wen, W., Xie, Y., & Chen, Y. (2016). Nvsim-VXs: An improved NVSim for variation aware STT-RAM simulation. 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), Austin Texas.
4. A Performance Conserving Approach for Reducing Memory Power Consumption in Multi-Core Systems
5. A perpendicular-anisotropy CoFeB–MgO magnetic tunnel junction
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1. Correction;International Journal of Electronics;2024-05-03
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