High-level design flow and environment for FPGA-based dynamic partial reconfiguration-Reference-Cited by-同舟云学术

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High-level design flow and environment for FPGA-based dynamic partial reconfiguration

Published:2017-02-27 Issue:8 Volume:104 Page:1254-1284
ISSN:0020-7217
Container-title:International Journal of Electronics
language:en
Short-container-title:International Journal of Electronics

Author:

Ben Abdelali Abdessalem¹²,Hannachi Marwa¹³,Krifa Mohamed Nidhal¹,Rabah Hassan³,Mtibaa Abdellatif¹

Affiliation:

1. Laboratory of electronics and microelectronics, University of Monastir, Monastir, Tunisia

2. High Institute of Informatics and Mathematics of Monastir, Monastir, Tunisia

3. Jean Lamour Institute, UMR7198, University of Lorraine, Vandoeuvre Les Nancy, France

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering

Link

https://www.tandfonline.com/doi/pdf/10.1080/00207217.2017.1293172

Reference26 articles.

1. Abel, N. (2010). Design and implementation of an object-oriented framework for dynamic partial reconfiguration. In 2010 International Conference on Field Programmable Logic and Applications (FPL), (pp. 1–9). doi: 10.1109/FPL.2010.55

2. Adequation and hardware implementation of the color structure descriptor for real-time temporal video segmentation

3. Introduction to Reconfigurable Computing

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