A Rail-to-Rail Topology for CMOS Neuron Cells with Analog Inputs-Output and Digital Weights
Author:
Affiliation:
1. Electrical and Electronic Engineering Department, Federal University of Santa Catarina, Florianópolis, SC, Brazil
2. Electrical Engineering Department, Federal University of Rio Grande do Sul, Porto Alegre, RS, Brazil
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
https://www.tandfonline.com/doi/pdf/10.1080/00207217.2021.1969440
Reference22 articles.
1. A 0.3-V Conductance-Based Silicon Neuron in 0.18 μm CMOS Process
2. Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations
3. Neuromorphic Hardware System for Visual Pattern Recognition With Memristor Array and CMOS Neuron
4. Design and VLSI implementation of a unified synapse-neuron architecture
5. An Analog CMOS Implementation for Multi-layer Perceptron With ReLU Activation
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