Design of universal logic gates using homo and hetero-junction double gate TFETs with pseudo-derived logic
Author:
Affiliation:
1. School of Electronics Engineering, VIT University, Chennai, India
2. Centre for Nano-Electronics & School of Electronics Engineering, Vit University, Chennai, India
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
https://www.tandfonline.com/doi/pdf/10.1080/00207217.2021.2025456
Reference50 articles.
1. A two-dimensional analytical subthreshold behavior analysis including hot-carrier effect for nanoscale Gate Stack Gate All Around (GASGAA) MOSFETs
2. 30-nm Tunnel FET With Improved Performance and Reduced Ambipolar Current
3. Heterojunction TFET Scaling and resonant-TFET for steep subthreshold slope at sub-9nm gate-length
4. TFET Inverters With n-/p-Devices on the Same Technology Platform for Low-Voltage/Low-Power Applications
5. TFET-Based Circuit Design Using the Transconductance Generation Efficiency $ {g}_{m}/ {I}_{d}$ Method
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1. Design and implementation of the logic gates using electrically doped configurable polarity control double gate tunnel FET;Physica Scripta;2024-02-22
2. Radiation study of TFET and JLFET-based devices and circuits: a comprehensive review on the device structure and sensitivity;Radiation Effects and Defects in Solids;2022-10-18
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