Energy efficient VLSI decoder chip with reduced PAPR in FECG monitoring-Reference-Cited by-同舟云学术

Energy efficient VLSI decoder chip with reduced PAPR in FECG monitoring

Published:2020-02-19 Issue:8 Volume:107 Page:1304-1323
ISSN:0020-7217
Container-title:International Journal of Electronics
language:en
Short-container-title:International Journal of Electronics

Author:

Preethi D¹,Valarmathi R S²,R Harikumar¹

Affiliation:

1. Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Erode, India

2. Department of Electronics and Communication Engineering, Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Chennai, India

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering

Link

https://www.tandfonline.com/doi/pdf/10.1080/00207217.2020.1726490

Reference27 articles.

1. VLSI implementation of MIMO detection using the sphere decoding algorithm

2. A First-Order Primal-Dual Algorithm for Convex Problems with Applications to Imaging

3. A hybrid imperialist competitive algorithm for minimizing makespan in a multi-processor open shop

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Designing of Power-Efficient CMOS Based Digital Decoder: An Architectural Variations and Comparative Insights;2023 International Conference on Next Generation Electronics (NEleX);2023-12-14

2. Field programmable gate array implementation of an adaptive filtering based noise reduction and enhanced compression technique for healthcare applications;Transactions on Emerging Telecommunications Technologies;2022-09-25

3. A Novel Energy-Efficient MIMO-OFDM Decoder Architecture with Error Detection;IETE Journal of Research;2021-02-08