Substrate noise evaluation for lightly doped 45nm N-MOSFET using physical simulation models-Reference-Cited by-同舟云学术

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Substrate noise evaluation for lightly doped 45nm N-MOSFET using physical simulation models

Published:2023-02-20 Issue:2 Volume:111 Page:338-359
ISSN:0020-7217
Container-title:International Journal of Electronics
language:en
Short-container-title:International Journal of Electronics

Author:

Sharma Sanjay¹,Yadav R. P.²,Janyani Vijay³

Affiliation:

1. Research Scholar, Department of Electronics and Communication Engineering, Malaviya National Institute of Technology Jaipur (MNIT), Jaipur, Rajasthan, India

2. Department of Electronics and Communication Engineering, Malaviya National Institute of Technology Jaipur (MNIT), Jaipur, Rajasthan, India

3. Department of Electronics and Communication Engineering, Malaviya National Institute of Technology Jaipur (MNIT), Jaipur, Rajasthan, 302017 India

Funder

no funds, grants, or other support were received during the preparation of this manuscript

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering

Link

https://www.tandfonline.com/doi/pdf/10.1080/00207217.2022.2164072

Reference27 articles.

1. Numerical analysis of Double Gate and Gate All Around MOSFETs with bulk trap states

2. Analysis and evaluation of noise coupling between through-silicon-vias

3. A millimeter‐wave scalable small signal model of RF CMOS transistor against number of fingers

4. NBTI and Irradiation Effects in P-Channel Power VDMOS Transistors

5. A network of SMG-8, SMG-9 and SMG-1 C-terminal insertion domain regulates UPF1 substrate recruitment and phosphorylation

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