Performance analysis of network-on-chip topologies
Author:
Affiliation:
1. Department of Electronics, Banasthali University, Tonk 304022, Rajasthan, India
2. Delhi Metro Rail Corporation Ltd., Delhi-110001, India
3. Department of Computer Science, Banasthali University, Tonk 304022, Rajasthan, India
Publisher
Informa UK Limited
Link
https://www.tandfonline.com/doi/pdf/10.1080/02522667.2017.1372145
Reference14 articles.
1. Deflection Routing in Hierarchical Mesh NoCs
2. Processor Tile Shapes and Interconnect Topologies for Dense On-Chip Networks
3. Topologies and routing strategies in MPSoC
4. A shortly connected mesh topology for high performance and energy efficient network-on-chip architectures
5. Performance analysis and comparison of 2×4 network on chip topology
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