A fault‐tolerant connected‐cycle‐based mesh architecture-Reference-Cited by-同舟云学术

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A fault‐tolerant connected‐cycle‐based mesh architecture

Published:2001-01 Issue:1 Volume:24 Page:103-112
ISSN:0253-3839
Container-title:Journal of the Chinese Institute of Engineers
language:en
Short-container-title:Journal of the Chinese Institute of Engineers

Author:

Huang Jyh‐Ming

Publisher

Informa UK Limited

Subject

General Engineering

Link

http://www.tandfonline.com/doi/pdf/10.1080/02533839.2001.9670611

Reference13 articles.

1. A taxonomy of reconfiguration techniques for fault-tolerant processor arrays

2. Reliability, reconfiguration, and spare allocation issues in binary-tree architectures based on multiple-level redundancy

3. A comprehensive reconfiguration scheme for fault-tolerant VLSI/WSI array processors

4. Chung, F.R.K., Leighton, F.T. and Rosenberg, A.L. “Diogenes: A Methodology for Designing Fault‐Tolerant VLSI Processor Arrays”. 13th Annual International Symposium on Fault‐Tolerant Computing. pp.26–32.

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