Power Efficient Hierarchical Scheduling for DSP Transformations

Abstract

In this paper, the problem of scheduling the computation of partial products in transformational Digital Signal Processing (DSP) algorithms, aiming at the minimization of the switching activity in data and address buses, is addressed. The problem is stated as a hierarchical scheduling problem. Two different optimization algorithms, which are based on the Travelling Salesman Problem (TSP), are defined. The proposed optimization algorithms are independent on the target architecture and can be adapted to take into account it. Experimental results obtained from the application of the proposed algorithms in various widely used DSP transformations, like Discrete Cosine Transform (DCT) and Discrete Fourier Transform (DFT), show that significant switching activity savings in data and address buses can be achieved, resulting in corresponding power savings. In addition, the differences between the two proposed methods are underlined, providing envisage for their suitable selection for implementation, in particular transformational algorithms and architectures.