Ultra-Low Specific On-Resistance Trench SOI LDMOS with a Floating Lateral Field Plate-Reference-Cited by-同舟云学术

Ultra-Low Specific On-Resistance Trench SOI LDMOS with a Floating Lateral Field Plate

Published:2017-03-23 Issue:4 Volume:35 Page:342-350
ISSN:0256-4602
Container-title:IETE Technical Review
language:en
Short-container-title:IETE Technical Review

Author:

Yang Dong¹,Hu Shengdong¹²,Huang Ye¹,Jiang Yuyu¹,Cheng Kun¹,Yuan Qi¹,Lei Jianmei²,Lin Zhi¹,Zhou Xichuan¹,Tang Fang¹

Affiliation:

1. Chongqing Engineering Laboratory of High Performance Integrated Circuits, College of Communication Engineering, Chongqing University, Chongqing, China

2. State Key Laboratory of Vehicle NVH and Safety Technology, China Automotive Engineering Research Institute Co. Ltd., Chongqing, China

Funder

National Natural Science Foundation of China

Open Funds of State Key Laboratory of Vehicle NVH and Safety Technology

Fundamental Research Funds for the Central Universities, China

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering

Link

https://www.tandfonline.com/doi/pdf/10.1080/02564602.2017.1299596

Reference25 articles.

1. A 2-D analytical model of SOI high-voltage devices with dual conduction layers

2. Improving breakdown, conductive, and thermal performances for SOI high voltage LDMOS using a partial compound buried layer

3. SJ/RESURF LDMOST

4. An Analytical Model of Triple RESURF Device with Linear P-layer Doping Profile

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