Improvements on binary coding using parallel computing

Author:

Fuentes P. Abascal,Quintas David García,Meana Jorge Jiménez

Publisher

Informa UK Limited

Subject

Applied Mathematics,Computational Theory and Mathematics,Computer Science Applications

Reference11 articles.

1. Abascal, P. and Tena, J. Algoritmos de búsqueda de un código corrector de errores realizando una estructura de acceso para compartir secretos. Proceedings of V RECSI. September 16–18, Málaga, Spain. Edited by: López Muñoz, F. J., Pastor Franco, J. and Troya Linero, J. M. pp.279–288. Málaga: IMIGRAF.

2. Gustafson, J. L. 1990. Fixed time, tiered memory, and superlinear speedup. Proceedings of the Fifth Distributed Memory Computing Conference. Volume II (DMCC5). April 8–121990, Charlestone, South Carolina. Edited by: Walker, D. W. and Stout, Q. F. pp.1255–1260. Los Alamitos, CA: IEEE Computer Society Press. Session 41: Performance Evaluation and Analysis

3. Modelling speedup (n) greater than n

4. Intel Corp.Quad-Core Intel Xeon Processor 5100 Series, August 2007. Available athttp://download.intel.com/design/Xeon/datashts/31335503.pdf

5. Intel Corp.Quad-Core Intel Xeon Processor 5400 Series, August 2008. Available athttp://download.intel.com/design/xeon/datashts/318589.pdf

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1. Solving time-varying nonlinear inequalities using continuous and discrete-time Zhang dynamics;International Journal of Computer Mathematics;2013-02-22

2. Applications of computational mathematics in science and engineering;International Journal of Computer Mathematics;2011-06

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