1. Guest Editors' Comments
2. CURRENT , W. , 1989 , A CMOS quaternary latch .Proceedings of the 19th I.E.E.E. Computer Society International Symposium of Multiple-Valued Logic, pp. 54 – 57 .
3. DIAWO , K. , and MOUFTAH , H. T. , 1987 , A three-valued CMOS arithmetic logic unit chip .Proceedings of the 17th I.E.E.E. Computer Society International Symposium of Multiple-Valued Logic, pp. 215 – 220 .
4. FREITAS , D. A. , and CURRENT , K. W. , 1983 , A quaternary logic encoder-decoder circuit design using CMOS . Proceedings of the 13th I.E.E.E. Computer Society International Symposium of Multiple-Valued Logic , pp. 190 – 195 .