Yield prediction via spatial modeling of clustered defect counts across a wafer map
Author:
Publisher
Informa UK Limited
Subject
Industrial and Manufacturing Engineering
Link
http://www.tandfonline.com/doi/pdf/10.1080/07408170701275335
Reference26 articles.
1. Defect analysis and yield degradation of integrated circuits
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1. Development of a spatial dimension-based taxonomy for classifying the defect patterns in a wafer bin map;Advanced Engineering Informatics;2024-04
2. Wafer Defect Pattern Labeling and Recognition Using Semi-Supervised Learning;IEEE Transactions on Semiconductor Manufacturing;2022-05
3. Prediction of per-batch yield rates in production based on maximum likelihood estimation of per-machine yield rates;Journal of Manufacturing Systems;2022-01
4. Two-level differential burn-in policy for spatially heterogeneous defect units in semiconductor manufacturing;Computers & Industrial Engineering;2021-12
5. Statistical Models of Overdispersed Spatial Defects for Predicting the Yield of Integrated Circuits;IEEE Transactions on Reliability;2020-06
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