Fabrication of sub-50-nm gate length n-metal–oxide–semiconductor field effect transistors and their electrical characteristics-Reference-Cited by-同舟云学术

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Fabrication of sub-50-nm gate length n-metal–oxide–semiconductor field effect transistors and their electrical characteristics

Published:1995-07 Issue:4 Volume:13 Page:1740
ISSN:0734-211X
Container-title:Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures
language:
Short-container-title:J. Vac. Sci. Technol. B

Author:

Ono Mizuki

Publisher

American Vacuum Society

Subject

General Engineering

Cited by 28 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Minimizing poly end cap pull back by application of DFM and advanced etch approaches for 65nm and 45 nm technologies;SPIE Proceedings;2007-03-16

3. Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning;Thin Solid Films;2006-05

4. CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING;International Journal of High Speed Electronics and Systems;2006-03

5. Sub-100 nm MOSFET fabrication with low temperature resist trimming process;Thin Solid Films;2004-09

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