Funder
H2020 European Research Council
Ministry of Defense
Deutsche Forschungsgemeinschaft
Publisher
Springer Science and Business Media LLC
Subject
Computer Networks and Communications,Software
Reference79 articles.
1. Agrawal, V.D.: Choice of tests for logic verification and equivalence checking and the use of fault simulation. In: Proceedings of the IEEE International Conference on VLSI Design, pp. 306–311. IEEE (2000)
2. Agrawal, V.D., Lee, D.: Characteristic polynomial method for verification and test of combinational circuits. In: Proceedings of the IEEE International Conference on VLSI Design, pp. 341–342. IEEE (1996)
3. Albartus, N., Hoffmann, M., Temme, S., Azriel, L., Paar, C.: DANA—universal dataflow analysis for gate-level netlist reverse engineering. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2020(4), 309–336 (2020)
4. Azriel, L., Ginosar, R., Gueron, S., Mendelson, A.: Using scan side channel to detect IP theft. IEEE Trans. Very Large Scale Integr. VLSI Syst. 25(12), 3268–3280 (2017)
5. Azriel, L., Ginosar, R., Mendelson, A.: Revealing on-chip proprietary security functions with scan side channel based reverse engineering. In: Proceedings of the 27th Edition o f the Great Lakes Symposium on VLSI, vol. Part F1277 (2017)
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