Author:
Brayton Robert K.,Hachtel Gary D.,Sangiovanni-Vincentelli Alberto,Somenzi Fabio,Aziz Adnan,Cheng Szu-Tsung,Edwards Stephen A.,Khatri Sunil P.,Kukimoto Yuji,Pardo Abelardo,Qadeer Shaz,Ranjan Rajeev K.,Sarwary Shaker,Shiple Thomas R.,Swamy Gitanjali,Villa Tiziano
Publisher
Springer Berlin Heidelberg
Reference5 articles.
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3. S.-T. Cheng. Compiling Verilog into automata. Tech. Rep. UCB/ERL M94/37, May 1994.
4. E.M. Sentovich et al. SIS: a system for sequential circuit synthesis. Tech. Rep. M92/41, May 1992.
5. VIS Home Page: http://www-cad.eecs.berkeley.edu/∼vis
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