Design of Environment-Friendly FIR Filter and Its Implementation on FPGA for Green Communication
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Publisher
Springer Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-16-1510-8_11
Reference12 articles.
1. Kumar, T., Pandey, B., Das, T.: Voltage scaling based energy efficient FIR filter design on FPGA. Int. J. Curr. Eng. Technol. 200–203 (2014)
2. Wang, X., Yu, M.: Power research of JPEG circuits in FPGA. in: Seventh International Conference on Intelligent Information Hiding and Multimedia Signal Processing, pp 206–208 (2011)
3. Behl, A., Gokhale, A., Sharma, N.: Design and implementation of fast booth-2 multiplier on Artix FPGA. In: International Conference on smart sustainable Intelligent Computing and Applications under ICITETM2020, pp 140–148 (2020)
4. Pandey, B., Kumar, T., Das, T., Yadav, R., Pandey, O.J.: Capacitance scaling based energy efficient FIR filter for digital signal processing. In: IEEE International Conference on Reliability Optimization & Information Technology (ICROIT) (2014)
5. Jose, I.: ACHA, computational structures for fast implementation of l-path and l-block digital filters. IEEE Trans. Circ. Syst. 36, 805–812 (1989)
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