Reduction of Kickback Noise in a High-Speed, Low-Power Domino Logic-Based Clocked Regenerative Comparator
Author:
Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-13-0212-1_46
Reference11 articles.
1. Babayan-mashhadi, Lotfi (2014) Analysis and design of a low-voltage low-power double-tail comparator. IEEE Trans Very Large Scale Integr (VLSI) Syst 22(2)
2. Goll B, Zimmermann H (2009) A comparator with reduced delay time in 65-nm CMOS for supply voltage down to 0.65 v. IEEE Trans Circuits Syst II, Exp Briefs 56(11):810–814
3. Mesgarani, Alam MN, Nelson FZ, Ay SU Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS. In: Proceedings of IEEE international midwest symposium circuits systems
4. Ay SU A sub-1 volt 10-bit supply boosted SAR ADC design in standard CMOS. Int J Analog Integr Circuits Sig Process 66
5. Maymandi-Nejad M, Sachdev M 1-bit quantiser with rail to rail input range for sub-1 V modulators. IEEE Electron Lett 39
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