An Efficient 8T GDI Enable Full Adder Design for Data Path Subsystem
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-3656-4_66
Reference13 articles.
1. Malipatil S, Maheshwari V, Chandra MB (2020) Area optimization of CMOS full adder design using 3T XOR. In: 2020 international conference on wireless communications signal processing and networking (WiSPNET). IEEE (2020)
2. Agarwal M, Agrawal N, Alam MA (2014) A new design of low power high speed hybrid CMOS full adder. In: 2014 international conference on signal processing and integrated networks (SPIN), pp 448–452 (2014)
3. Khan AA, Pandey S, Pathak J (2014) A review paper on 3-T XOR cells and 8-T adder design in cadence 180 nm. In: International conference for convergence for technology-2014. IEEE, pp 1–6
4. Chowdhury SR, Banerjee A, Roy A, Saha H (2008) A high speed 8 transistor full adder design using novel 3 transistor XOR gates. Int J Electron Circ Syst 2(4):217–223
5. Kadu CP, Sharma M (2017) Area-efficient high-speed hybrid 1-bit full adder circuit using modified XNOR gate. In: 2017 international conference on information, communication, instrumentation and control (ICICIC). IEEE, pp 1–5
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